The present invention relates to a semiconductor device and a method for manufacturing the same. For example, the present invention is concerned with a DRAM package (a semiconductor device with one or plural DRAM chips mounted thereon will hereinafter be referred to herein as "DRAM package") comprising plural DRAM (Dynamic Random Access Memory) chips (a semiconductor chip capable of functioning as DRAM will hereinafter be referred to herein as "DRAM chip"), as well as a technique which is particularly useful in producing such DRAM package.
A DRAM chip having as a basic configuration a memory array comprising lattice-like arranged dynamic memory cells as well as a DRAM package having such DRAM chip as a basic configuration are known. In the conventional DRAM package, usually, one DRAM chip is mounted thereon and bonding pads used therein are connected to corresponding leads of a lead frame integral with external terminals.
As to the DRAM package carrying a single DRAM chip thereon, it is described, for example, in U.S. Ser. No. 496,280 filed Mar. 20, 1990.
Recent success towards higher integration density and larger memory capacity of a DRAM chip has been remarkable and corresponding the chip area has been increasing. At the same time, the DRAM package which carries a DRAM chip thereon also tends to become larger in size. As a result, there has developed a problem that the packaging efficiency of a memory system or the like comprising a DRAM package has not greatly improved.
To cope with the above problem, as shown in FIGS. 65 to 67, there been proposed several methods for mounting on a single package a plurality of sub chips (in the case where one package is composed of plural semiconductor chips, those plural constituent semiconductor chips will each be referred to herein a "sub chip"). More particularly, in FIG. 65, a plurality of sub chips 1E to 1I are mounted on the surface of a circuit board 7A. In FIG. 66, first a relatively large sub chip 1J is mounted on a lead frame 3, then two relatively small sub chips 1K and 1L are mounted as adjacently disposed sub chips on the sub chip 1J. Corresponding pads of the sub chips 1J and 1K, 1L are connected together through a solder bump 10. Further, bonding pads of the sub chip 1J are connected to corresponding external terminals, i.e., outer leads 3B, through bonding wires 5. On the other hand, in FIG. 67, first a sub chip 1N is die-bonded onto a circuit board 7B, and pads provided on the sub chip 1N are bonded to corresponding metallized portions 11 of the circuit board 7B through bonding wires 8. Then, the sub chip 1N is coated with a molding resin 9, and after the surface of the coating is flattened, a sub chip 1M is laminated onto the thus-flattened surface of the coating.
The chip mounting methods illustrated in FIGS. 66 and 67 are described in Japanese Patent Laid Open Nos. 284951/86 and 283634/87, respectively.